The present disclosure relates to a storage device that includes a memory cell having a storage element and a switching element, and particularly to a storage device and an information rerecording method for rerecording by verification control.
In information equipments such as a computer, a high density DRAM (Dynamic Random Access Memory) capable of high speed operation is widely used. However, in the DRAM, there is a problem that the manufacturing cost is high, since the manufacturing process is more complicated than that of a general logical circuit, a general signal processing circuit or the like used for electronic devices. Further, since the DRAM is a volatile memory in which information is not retained if the power is turned off, it is necessary to perform refresh operation frequently.
Thus, as a nonvolatile memory in which information is retained even if the power is turned off, for example, an FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetoresistive Random Access Memory) and the like have been proposed. In these memories, even if power is not supplied, written information is able to be retained for a long time. In addition, in these memories, it is not necessary to perform refresh operation, and thus power consumption is able to be decreased by just that much. However, there is a problem that miniaturization is not easy in the FeRAM, while there is a problem that a writing current is large in the MRAM (for example, Nonpatent Document 1).
Therefore, as a memory suitable for speeding up the data writing speed, a new type storage device as illustrated in FIG. 15 and FIG. 16 has been proposed.
FIG. 15 illustrates a memory cell 100 of the storage device. The memory cell 100 includes a variable resistive element 110 whose cross sectional structure is illustrated in FIG. 16 and an MOS transistor 120 (switching element). The variable resistive element 110 is formed by layering an electrode 111, an ion source layer 112, a high resistive layer 113, and an electrode 114. The electrode 111 is electrically connected to a bit line BLR, and the electrode 114 is electrically connected to one terminal of the MOS transistor 120, respectively. The other terminal of the MOS transistor 120 is electrically connected to a bit line BLT, and a gate of the MOS transistor 120 is electrically connected to a word line WL, respectively.
In the storage device, when a voltage is applied to the electrode 114 and the electrode 111 so that a current is flown from the ion source layer 112 to the high resistive layer 113, state of the high resistive layer 113 is changed to low resistance, and data is written. By contraries, when a voltage is applied to the electrode 114 and the electrode 111 so that a current is flown from the high resistive layer 113 to the ion source layer 112, state of the high resistive layer 113 is changed to high resistance, and data is erased.
Compared to the existing nonvolatile memory or the like, the storage device has features that no element size dependence exists since the memory cell is able to be structured by a simple structure, and the storage device is good at scaling since a large signal is able to be obtained. Further, the storage device has a large advantage that by controlling a recording current and a recording voltage, multiple values are able to be recorded, that is, 3 bit or more data is able to be stored in one memory cell (Patent document 1).    Nonpatent document 1: Nikkei Electronics, issue date: Jul. 16, 2007, p. 98    Patent document 1: Japanese Unexamined Patent Application Publication No. 2005-235360
However, for recording in the foregoing new type of storage device, it is necessary to properly adjust a resistance value level for every writing operation for every cell. Examples of techniques thereof include a method in which verification reading and rewriting are combined (hereinafter collectively and simply referred to as verification). That is, in such a method, verification reading is performed after writing operation. In the case of desired low resistance, it is determined that writing has succeeded and writing operation is finished. Meanwhile, in the case of high resistance exceeding the desired value, it is determined that writing has failed and rewriting is performed. Such a cycle is repeated until a certain upper limit number of cycles is completed. To obtain stable verification control, ability of adjusting the resistance value level should be improved.
In view of the foregoing problem, it is desirable to provide a storage device and an information rerecording method that improves ability of adjusting a resistance value level in recording and enables stable verification control.